Moving data to DX register, overflow cannot be evaluated - 8086
You can only use 16 bit offsets. You will need to set a segment register to an appropriate base address and use an adjusted offset that fits into 16 bits. PS: you don't need to load dl and dh separately....
Comparing 2 registers, each containing a character LC-3 Assembly
assembly,cpu-registers,subtraction,lc3
There is no direct operator to subtract using LC3. You need to use 2's compliment. R1 = R2-R3; //This is not possible. // using 2's Compliment method R1 <- NOT R3; R1 <- R1+1; R1 <- R2+R1; Register R1 will have the subtraction result. You can use your comparison code...
x86 64 AT&T , moving part of register into another register
indexing,x86,cpu-registers,mov
You can shift the bytes in one at a time, like this: ; Calculate first dl ... mov %dl,%bl ; Calculate next dl ... shlq $8,%rbx mov %dl,%bl ; Calculate next dl ... shlq $8,%rbx mov %dl,%bl etc. This assumes that you want the first byte in the msb, and...
How to move value of DL and DH to AX and BX register in NASM?
assembly,x86,nasm,cpu-registers
Those register combinations are forbidden. Use: mov al, dl mov bl, dh You might find it useful to read the documentation....
Moving AX into CL - Invalid combination of opcode and operands
assembly,cpu-registers,bootloader
The problem, as the comment to your original question states, is that you're trying to move the contents of a 16 bit register into an 8 bit register. You can't do that because the registers are different sizes. If you want to move data from the AX register into the...
How Will Register Transfer work in a Quantum computer ?
cpu-registers,cpu-architecture,quantum-computing
The no-cloning theorem says it's not possible to copy quantum states (pure or mixed). If you want a copy, you have to measure the qubits, collapsing them to classical information, and then copying that - but you loose almost all the information encoded in the system and you're left with...
Assembly - Combining and storing characters from string with XOR
assembly,hex,masm,xor,cpu-registers
OP asked I'm not sure how "Joe Smith" translates to 0000002B in hexadecimal. char ASCII binary hex ----- ----- --------- --- J 74 0100 1010 4A o 111 0110 1111 6F e 101 0110 0101 65 (space) 32 0010 0000 20 S 83 0101 0011 53 m 109 0110 1101...
Which of these two operations on an 8086 CPU will be faster in execution and why?
memory,memory-address,cpu-registers,8086,segment
A transfer from memory to register on a 8086 CPU takes 8 clocks + the clocks needed to calculate the effective address. mov ax,[0x000B] ; Executes in 8+6+4 clocks Aligning data on a word boundary ensures faster fetch times so one would expect that line 2 could be faster. And...
Why am I getting an “expected register or immediate value” error?
assembly,cpu-registers,computer-architecture,machine-code,lc3
You're getting this error because the LC3's state machine only has two versions of the ADD command. ADD R1, R2, R3 ADD R1, R2, #7 You can see that we can add registers together or we can use ADD immediate. ADD immediate is where we use the last operand as...
How can I know that my CPU shares the vector registers among the cores or each core has its private ones
cpu,cpu-registers,cpu-architecture
Judging from your comments in another reply, it appears you're referring to the Xeon Phi. If I understand correctly, you're asking if each thread has its own private set of vector registers? The answer is yes! To clarify a little further, the Xeon Phi has about 50 cores each with...
Bit field extract with struct in c
c,struct,bit-manipulation,intel,cpu-registers
You have tried two ways to do the same thing, and I wouldn't trust either of them. First, bit fields. Don't use them! The ordering of bit fields is unreliable, the behaviour of anything other than unsigned int is unreliable, the distribution of bit fields across struct members is unreliable....
How to save a group of registers and restore them later?
assembly,arm,cpu-registers,instruction-set
The first operand of LDM/STM (r0 in your examples) is the base register. That register holds the address in memory where the values in the register list will be stored. So, for example, when you STMIB r0!,{r1-r3} with r0==0x9000 you'll store the value of r1 at address 0x9004, r2 at...
ASCII and 64bit Registers Assembly
assembly,64bit,ascii,cpu-registers
Because you've specified 1024 as the length which means the read syscall is getting two bytes, the 31h representing the character '1', and the 0ah representing the newline. If you only want one character, only ask for one character, not 1024. And, if you try to get the full width...
Unexpected result of assembly program
assembly,interrupt,masm,cpu-registers
Your tutorial deals with .MODEL TINY to produce a .com-executable. You use .MODEL SMALL and produce an .exe-executable. For .MODEL SMALL you must explicitely set the DS-register which points by default to the PSP (not to .DATA): .MODEL SMALL .STACK 1000H ; Mor stack, less trouble .DATA msg db "123123.$"...
Reserve bytes in stack: x86 Assembly (64 bit)
Is "$32" means 32 bytes ?($number means constant ?) If yes then how are we allocating 32 bytes on 64 bit register? These 32 bytes are not allocated on 64 bit register. They are allocated on the stack. By lowering the stackpointer (which is in %rsp) the address range...
No LR and SPSR for EL0 in Aarch64
exception-handling,arm,cpu-registers,arm64
By design exceptions cannnot target EL0, so if it can't ever take an exception then it has no use for the machinery to be able to return from one. To expand on the reasoning a bit (glossing over the optional and more special-purpose higher exception levels), the basic design is...
Trouble creating an array loop in Y86 Assembly
arrays,loops,assembly,cpu-registers,y86
y86 does not support the full x86 effective address syntax with the index and scale, it only allows displacement(base). You have to perform the address calculation yourself. The y86 assembler doesn't support .comm either, just define your data using .long...
Where is -32768 coming from?
assembly,load,cpu-registers,computer-architecture,lc3
In KBSR (keyboard status register) bit 15 is set when a key is read, so you get 0b1000_0000_0000_0000 (or 0x8000) ... which - interpreted as a 2's complemented negative number - happens to be -32768 decimal.
computing the actual address from assembly in cmp
c,assembly,gdb,cpu-registers,cmp
If you don't know at&t syntax, switch gdb to intel syntax using set disassembly-flavor intel. Then you will see this expression is really rbp+rbx*4+4. Then read gdb help and you will find the x (examine memory) command and that you can access registers using $ prefix. Putting all this together,...
The CPU, BIOS, or OS does the IO port address assigment?
io,operating-system,cpu-registers,bios
Normally the addresses of addressable I/O are assigned by hardware. Literally, there is logic circuitry (either internal to the processor or external) which watches the bus for a specific address, and causes a peripheral function register to latch the data which is being written off the bus, or drive the...
Substraction in assembly 8086 sets wrong flags
assembly,binary,cpu,cpu-registers,8086
the idea that sub is the same as +(- your number). To the CPU this is not true. Your first number and second number are equal. The fact that you as a human understand that the second number is a negative one does not make a difference to the processor....
If the CS register of a 8086 has the value 0xA000, what is the range of the physical addresses of the associated segment?
memory,memory-address,cpu-registers,8086,segment
Shift left 4 bits. 0xa0000 + whatever value is hqving CS applied. Since the cpu registers and other values are 16-bit, you get 0xAxxxx where xxxx is a 16 bit value. That is, the segment register specifies which 64k can be addressed. By windowing like that, you can get a...
How does CPUs runs Multiple Applications at a Time with a limited number of Registers?
On context switches (in particular, when running some other process), the operating system kernel is saving the process state (notably inside its scheduler for preemptive multi-tasking), notably the registers, somewhere in memory. The hardware is able to handle interrupts often by saving at least some registers in memory. If you...
Assembly - compiler will not see my inline changes?
linux,assembly,x86-64,cpu-registers,att
Since you specified a 16 bit type, but printf expects 32 bit integers, your result needs to be sign extended which is what that code does. Nevertheless, if you used the proper format for printf both versions should produce identical output. As usual, you don't need inline asm for a...
What happens when the eip register reaches its maximum value?
assembly,x86,cpu,cpu-registers,eip
Typically, you don't let it happen. %eip doesn't increment unconditionally; it's affected by flow control instructions (like jmp, call, bcc, etc). In practice, this behavior is unpredictable. On some CPUs, overflowing %eip causes a fault. On some others, it silently wraps around to zero. These discrepancies led to a famous...
Which are the operands in Lc3 instruction?
assembly,cpu,cpu-registers,computer-architecture,lc3
"operands (who the computer is expected to do it to)." - pg116 "The LD instruction requires two operands." - pg180 The LD command requires both a register and a label. The label is technically a PCoffset9. "operands can be obtained from registers, from memory, or they may be literal" -...
Simple register allocation scheme for x86
assembly,compiler-construction,x86,allocation,cpu-registers
Rather than computing the result always into EAX, think in terms of computing the result into a destination location that may be either a register or a memory location. In pseudocode: for each 3AC instruction I Look up the set S of places that hold operands of I R =...
In IA-32 assembly language, can IDTR, GDTR or LDTR be modified or 'loaded' without the LIDT, LGDT and LLDT instructions?
The IDTR, GDTR or LDTR can be modified by: LIDT, LGDT and LLDT instructions entering system management mode, modifying the values in the "state save" area, then leaving system management mode to cause the modified values to be loaded using hardware virtualisation extensions, where host is able to modify the...
Index register in cpu (Computer org. and arc.)
indexing,cpu,cpu-registers,computer-architecture,cpu-architecture
A register can hold any value that fits in the number of bits it has. What makes the value negative or not is the way you treat it. The question you should be asking yourself is - does your basic CPU support signed arithmetic operations, and how does it encode...
Assembly - inline asm - copy from one array to another?
linux,assembly,x86-64,cpu-registers,att
Now close the ABI doc, and open the intel manual, basic architecture and the instruction set reference of course :-> First of all, mov does not accept two memory operands, you have to go through a register or use the specialized string move movs. Second, in the effective address you...
How can I ivestigate use of the register keyword in C?
Today, with optimizing compilers (like GCC with -O1 at least), the register keyword is indeed deprecated. Its only meaning is to forbid taking the address of such a declared variable. In other words, register int r; printf("[email protected]%p\n", &r); // WRONG: address of register variable should not compile. GCC also provides...
What's wrong with register keyword in C++? [duplicate]
c++,cpu-registers,c++1z,storage-class-specifier
You've pretty much answered your own question: I think modern compilers are very smart so they implicitly optimizes frequently used variables for speed (fast access) & puts them in CPU register. That's precisely the point—optimisers are so good at register allocation nowadays that any attempt from the programmer to enforce...
Arithmetic operations in AT&T assembly (adding memory and a register)
when we read the value to perform the addition (%eax) gives us back 0xFF, but when we use (%eax) as the destiation of addition, we write to 0x100. Can someone explain this please? In both cases, using (%eax) as an operand means referencing memory at the address contained in...
Shouldn't R3 hold address x3307?
assembly,cpu-registers,computer-architecture,machine-code,lc3
PC-relative offsets are applied on top of the already incremented PC, that is the "after" value of the PC, or in other words, the address of the following instruction.
Difference between memory and register
memory,assembly,cpu-registers,instructions,mov
In this syntax, brackets around a register means a memory location is used (as source or destination, according to the instruction) with starting address specified at the register (EAX in your case). For example, if EAX contained 1344 before the instruction, value from EBX is copied to logical memory addresses...
Last Reboot detection on PhyCORE-AM335x-PD13.1.2 Linux 3.2
linux,driver,embedded-linux,cpu-registers,watchdog
I start by using terminal command devmem 0x44E00F08 (busybox) to see if reading the physical memory will work then I use mmap() to read the PRM_RSTST register and know if the last reset was watchdog reset.
Load two 64-bit integers into lower & upper xmm, respectively
Being limited to SSSE3 means no pinsrq, but you can do this: movq xmm1, r8 pslldq xmm1, 8 movq xmm0, rdx por xmm0, xmm1 There are many other ways, but I can't think of anything faster right now. Maybe this, if it doesn't have bypass delays: movq xmm1, r8 movq...
Sparc assembly - Global registers not consistent throughout functions call
From the SPARC Assembly Language Reference Manual (https://docs.oracle.com/cd/E26502_01/html/E28387/toc.html) 6.2 Register Usage The global registers %g0-%g7 are more complicated. The %g0 register is always zero. The %g6 and %g7 are always reserved for the operating system, so assembly code should not modify them. The other global registers, %g1-%g5, are caller saves,...
How does LEA instruction store address of A?
assembly,load,cpu-registers,computer-architecture,lc3
Anytime you see a PCoffset as an opcode operand LEA R2, A ; Loads the memory location of A into R2 ; LEA, DR, PCoffset9 It's telling you that when your code is assembled it doesn't actually place the label 'A' into your LEA command. Take the following code: .ORIG...
Access Write Violation When Accessing the Value of a Register in assembly x86
assembly,x86,access-violation,masm,cpu-registers
Not sure what you are doing, but since it looks like you want dereference a mem address, you must use addr for local vars to get/pass that address. main PROC LOCAL thesize:DWORD mov thesize, 3 ; INVOKE compare, thesize, thesize ; same as: ; push 3 ; push 3 ;...
How to use MIPS $k0 and $k1 registers
An interrupt handler must save any general - purpose registers that it is going to use (to be restored at return). But to do so requires you to modify at least one register first (something like sw $t0, saved_t0 expands to two machine instructions using $at). This situation is resolved...
x86 assembly language with ebx and bh
xor ebx,ebx mov bh ,0x04;how to change that "bh" to "ebx" ,and keep codes same meaning? Assuming I understand you correctly, what you want is this: mov ebx, 0x0400 (bh is the upper 8 bits of bx, which is itself the lower 16 bits of ebx. So the value...
Show cpu cache and register contents during debugging
c++,memory-management,visualization,cpu-registers,cpu-cache
I'm afraid you won't be able to look directly into the cache state during runtime, since the act of looking, especially if breakpoints are involved, or some code that would manage this inspection, would greatly impact on the cache state, practically destroying what you were trying to inspect. Worse -...
gcc incorrectly reusing registers in inline asm
c,gcc,optimization,inline-assembly,cpu-registers
The problem is that the 'clobbers' list is a list of register names, or the special strings "cc" and "memory". Since there is no register called "0", having this in the clobbers list is meaningless. Unfortuately gcc does not give you a warning about this. Instead, as the gcc docs...
GDB info registers command - Second column of output
The info registers command prints out registers in both raw format (hex) and natural format. The natural format is based on the type of the register, declared in xml files in gdb's source code. For example, i386/64bit-core.xml contains: <reg name="rax" bitsize="64" type="int64"/> <reg name="rbx" bitsize="64" type="int64"/> <reg name="rcx" bitsize="64" type="int64"/>...
Free Pascal accepting MOVQ xmm, r
assembly,cpu-registers,freepascal
When in doubt always consult the official reference, not some obscure web page. This is what the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z says: 66 REX.W 0F 6E /r MOVQ xmm, r/m64 SSE2 Move quadword from r/m64 to...
(Lower level of C++) When using “cout” on a piece of data, were does it go to before being displayed on screen?
The lower level stuff of C++ is platform dependent. For example, reading a character from the keyboard. Some platforms don't have keyboards. Some platforms send messages when a character arrives, others wait (poll the input port). Let's talk one level down from the high level language. For cin, the underlying...
What does stripping off the ASCII template mean?
assembly,ascii,cpu-registers,computer-architecture,lc3
As you noticed, operations are performed on ASCII values of entered characters. In assembly, if you read characters from keyboard, you really get their ASCII values in registers, so let's say you enter 2 and 3 and want to add them, then you are really adding 50+51. You have to...
Changing the sign bit of a register in assembly 8086
XOR operation the constant 0x8000 (for 16bit) with the register you want to change. Bit of googling: xor Bitwise logical XOR Syntax: xor dest, src dest: register or memory src: register, memory, or immediate Action: dest = dest ^ src Flags Affected: OF=0, SF, ZF, AF=?, PF, CF=0 ...
CMSIS register values
arm,embedded,cpu-registers,cmsis
If you look in your CMSIS header, you'll see all the structure definitions. Here's an example from my current project: typedef struct { __IO uint32_t DATA; /*!< Port A Data Register */ __IO uint32_t CR; /*!< Port A Output Control Register */ __IO uint32_t FR1; /*!< Port A Function Register...
Register Allocation in Compilers
compiler-construction,code-generation,cpu-registers
Hardware registers are expensive (both in terms of die area and the number of instruction bits required to address them), and therefore generally quite few in number. Spilling occurs when the number of live variables (or, more accurately, the number of live ranges) at a given program point exceeds the...
GCC disable RBP RSP register optimiziton when using -O*?
gcc,optimization,cpu-registers,register-allocation
-fomit-frame-pointer is enabled by default at optimization levels -O, -O2, -O3, -Os You need to use -fno-omit-frame-pointer However there are not much reasons to keep the frame pointer unless you're debugging and need to trace the stack frame. In that case, use -Og instead...