Or Reduce An Array of Vectors

Needs to be placed on a real board, so will have to synthesize.

Using an old VHDL, libraries included:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;

Some signals:

type my_array is array (N-1 downto 0) of std_logic_vector(31 downto 0);
signal enable : my_array;
signal ored_enable: std_logic_vector(31 downto 0);

Signals get joined up in a generator:

my_gen: for i in 0 to (N-1) generate

    woah: entity work.my_entity

            port map(
                    clk => clk,
                    enable => enable(i)
                    );


 end generate;

ored_enable <= or_reduce(enable); -- this fails

I'm just trying to create a std_logic_vector which holds the ored signals from the array. Any ideas how I can simply achieve this?

Best How To :

First, I expect your last line to be a typo and read

ored_enable <= or_reduce(enable);

But this wouldn't work since or_reduce is only defined for std_logic_vector, not array of std_logic_vector. You can create your own reduce function:

function or_reduce(a : my_array) return std_logic_vector is
    variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
    for i in a'range loop
        ret := ret or a(i);
    end loop;

    return ret;
end function or_reduce;

Just put it in your architecture's declarations and it should work.

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