Needs to be placed on a real board, so will have to synthesize.
Using an old VHDL, libraries included:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_misc.all;
type my_array is array (N-1 downto 0) of std_logic_vector(31 downto 0); signal enable : my_array; signal ored_enable: std_logic_vector(31 downto 0);
Signals get joined up in a generator:
my_gen: for i in 0 to (N-1) generate woah: entity work.my_entity port map( clk => clk, enable => enable(i) ); end generate; ored_enable <= or_reduce(enable); -- this fails
I'm just trying to create a
std_logic_vector which holds the ored signals from the array. Any ideas how I can simply achieve this?