How do I concatenate parameters and integers in verilog
If you can use SystemVerilog, then this is what you can write mem_memory #(.MIFNAME($sformatf("mem_%0d_init.mif",i)) u_mem (...); Otherwise you will need to get creative with parameters genvar i; for (i=0; i<=4; i=i+1) begin : MEM_INST localparam [7:0] index = "0"+i; mem_memory #(.MIFNAME({"mem_",index,"_init.mif"}) u_mem (...); end endgenerate ...
Use dma transfert with Cyclone V Avalon-MM for PCIe
dma,altera,pci-e,quartus-ii,qsys
I finally managed to make DMA request with the «Cyclone V Avalon-MM for PCIe» altera core-ip. Then yes it's possible. On my Linux system, rootcomplex (RC) is included under i.MX6 with Linux operating system. Then most of the tricks are on the Linux side in fact. Under the Linux driver a...
C to Fpga error with LCD under Altera DE2-70 board
altera,hardware-interface,systemc
I found the answer, this library is no more supported in the new DK5 the best way to use it is to convert to hex then display it as following: /* Convert to HEX*/ y =5; Unsigned 8 decode_to_hex(unsigned 4 x) { } /*Then display using */ Line = (decode_to_hex(y)<-8)...
QuartusII 14.1.0 Debian Linux crash
linux,debian,altera,quartus-ii
It's a known bug in Altera. They provided me a patch to correct it : quartusii-14.1-0.19-linux.run The patch can be found on altera support website : rd01272015_37 I applied it and quartus work well now. I think they will publish this correction soon....
Verilog module instantiation
Looking over the code you posted in your comment, the issue is from instantiating your module inside your always @(posedge clk) block on line 70. You never instantiate modules inside of procedural blocks (always, initial, etc). As Verilog is a Hardware Descriptive Language, you have to be in the mindset...
VHDL testbench for Modelsim (Altera)
[email protected]: ghdl -a quarter_round.vhdl [email protected]: ghdl -e quarter_round_vhd_tst quarter_round.vhdl:100:1: type of signal interface "y" from component "quarter_round" and port "y" from entity "quarter_round" are not compatible for an association quarter_round.vhdl:100:1: type of signal interface "z" from component "quarter_round" and port "z" from entity "quarter_round" are not compatible for an...
Correct arithmetic(cycle) shift in verilog
math,verilog,cycle,shift,altera
<<< and >>> are signed shift operators - ie 0xF0 >>> 1 = 0xF8 vs 0xF0 >> 1 = 0x78. Right shifting will beahve differently, but the <<< will be the same as <<. To do a cyclic right shift, use tempred <= {tempred[0],tempred[11:1]}; instead....
Inferred RAM doesn't initialize in ModelSim Altera edition
It looks like Modelsim may have a "mem load" command you can use at the start of your simulation in order to initialize the memory. Take a look at the end of this thread: Initialization altsyncram...
Edit top verilog component generated by Qsys
Ok, I found the solution. In fact, I selected design.qsys as «top-level». Doing this regenerate all HDL code. To avoid this, adding design.qip is a prefered way. This file can be found under the directory : design/synthesis/design.qip
VHDL integer range inclusive? Difference in FPGA vs. simulation
This happens because the line ledCounter <= ledCounter + 1 happens before the comparaison. Even if ledCounter's value won't actually reach 25000001, since overridden by the following statements, at this point it is scheduled to reach it, causing the simulation error. You can solve it easily by moving the increment...
Does Quartus II support line.all?
See Quartus II VHDL Support, Section 14 Predefined language environment, the table entry 14.3, Construct TEXTIO, the rightmost column VHDL 1993 Support: Supported. File I/O cannot be synthesized; therefore, calls to TEXTIO functions are ignored. If you can't use TEXTIO for synthesis you could imagine a pointer to a line...