How to Programming with Fpga

For one, your arrow points in the wrong direction. For port associations, always use =>, regardless of input or output ports. Second: the when/else construct is not an expression like a?x:y is in C. It is specific to a when/else signal assignment: http://www.sigasi.com/content/signal-assignments-vhdl-withselect-whenelse-and-case You need to either use an intermediate...

verilog code to convert binary input into residue number system

In [email protected](posedge clk) use non-blocking assignments (<=). The way you have defined initial values is not typical. Either use and initial block or a reset. initial begin dout0=9'd0; dout1=9'd0; dout2=9'd0; dout3=9'd0; dout4=9'd0; dout5=9'd0; dout6=9'd0; dout7=9'd0; mod30=3'd0; mod31=3'd0; mod32=3'd0; mod33=3'd0; mod34=3'd0; mod35=3'd0; mod36=3'd0; mod37=3'd0; ... end Or [email protected](posedge clk, negedge rst_n)...

Buffering an input parameter to the process statement

verilog,fpga,system-verilog,quartus-ii

Reassigning the clock should be avoided, due to the reason of delta cycle delay that you describe. It will have no effect on the synthesis result, but it is likely to cause problems in simulation, for example if several nested modules does reassigning of the clock, whereby the clock can...

verilog $readmemh takes too much time for 50x50 pixel rgb image

First, some background: It's likely you're getting "Timing requirements not met" because of the size of the image - 50x50x8x3 is a fair number of storage bits, moreso if it's attempting to store them into logic instead of on-chip RAM. A 640x480 image is 900 kB, so only the biggest...

What is the difference between these verilog codes?

fpga,verification,system-verilog,assertion

Your first example uses continuous assignment to set the value of led to the value of switch. It's like connecting led and switch directly with a wire. Whenever switch changes, led also changes. Your second example does the same thing but uses an always block. always blocks have a sensitivity...

Can I access delayed value in SystemVerilog assertion

You can use the $past(...) system task. Using $past(rdaddress) will return the value of rdaddress that was sampled in the previous cycle. You can specify how many cycle in the past to go with the second argument. In your case, calling $past(rdaddress, 2) will return the value of rdaddress 2...

Verilog Vending machine FSM

verilog,fpga,hdl

I'm not sure why you are using: always @(current_state | ((quarter ^ nickel) ^ dime)) the standard coding style would be to use: always @(current_state or quarter or nickel or dime) With Verilog 2001 or System Verilog you can use a comma separated sensitivity list as follows: always @(current_state, quarter,...

My verilog VGA driver causes the screen to flicker (Basys2)

verilog,fpga,system-verilog,xilinx,vga

I'm posting this as an answer because I cannot put a photo in a comment. Is this what your design looks like? My only guess ATM is that you might have misplaced some ports during instantiation of vga_driver and/or map_generator (if you used the old style instantiation). Nevertheless, I'm going...

Non Blocking or Blocking assignment for a buffer?

buffer,verilog,fpga,fifo

Both the blocks are different. When you use blocking assignments, the next statement does not begin executing until the assignment has finished. x = #5 y + z; This statement is executed as follows: Evaluates the RHS expression and save the result Wait for the specified delay Perform assignment So...

How to prevent ISE compiler from optmizing away my array?

verilog,fpga,xilinx-ise

The reason your design is being synthesized away is because you have not described any logic in your module. The only block in your design is an initial block which is typically not used in synthesis except in limited cases; the construct mainly used for testbenches in simulation (running the...

Interpret G-code into motor control signals

c++,c,embedded,verilog,fpga

There are many open source implementations of G-code interpreters for 3D printers and home-made CNC machines. Even though there is no universal standard (as Hans mentions in comments), the open source community arrived at a consensus that seems to be generally accepted (description can be found on reprap wiki). Reprap...

Module without an EN - VHDL

It is perfectly ok to have a component without moduleEN signal. In fact, most of the modules I have seen do not have an enable signal. However, if you plan to reset a submodule in runtime, it is more reliable to use a synchronous reset signal: process(clock, reset) begin if...

How to assign pins to natural type of ports in Xilinx

Unfortunately, the one place where you can't use type natural is top level ports, where they are mapped to physical device pins. This is because you need to connect each individual bit of the signal to its own pin, so you need some type that represents the signal as an...

VHDL code not running properly on Nexys2

You are not changing the value for the output that is not selected, so it remains in the state it has been assigned last. Also, your code your code will only ever have an effect on the rising edge of the clock, so the sensitivity list can be reduced to...

Synthesis: Implementing a delay signal using a counter on power-up of FPGA

linux,performance,raspberry-pi,fpga

For some reason, setting the initial values by the declarations seems to be the problem with this FPGA/toolset (synopsis Synplify and the FPGA is Actel A3PN250) even if it works in modelsim simulation. The following code does what I want -- Set an output high after the FPGA is turned...

Send numerical data via TCP/IP ethernet

c++,c,winsock,fpga

This is not a question of TCP vs UDP. First, to send a single float value, you don't reinterpret it as an address, but take the address of the float iResult = send(ConnectSocket, &f, (int) sizeof(f), 0); But this works only, if you have the same architecture on both ends...

What is the cause of Vivados 'synth 8-1027' error?

vhdl,fpga,xilinx,vivado

Vivado parses all files. Even those which are not used! My ISE project had a old backup file with a package named 'DMATest' inside it. This should explain why DMATest was reanalyzed and DMATest is not an entity - it was overridden by the package....

Connect parallellas and a pi via fpga and 1/0 pins

The solution depends on the bandwidth and latency requirements. You are right that FPGA provides the largest bandwidth and lowest latency. However, do you really need such good performance? Maybe USB or Ethernet connections are good enough. For the FPGA solution, consider the secondary pi and parallella as two peripherals...

Passing parameters to Verilog modules

module,verilog,fpga,parameterization

The defparam statement is scheduled for deprecation. The IEEE Std 1800-2012, Annex C (Deprecation), section "C.4.1 Defparam statements" states: users are strongly encouraged to migrate their code to use one of the alternate methods of parameter redefinition. Many features of Verilog are vendor-dependent....

Code for 8 point DCT using shifters and adders

The warning messages are self descriptive and you are only dealing with four types: WARNING:Xst:646 - Signal <signal_name> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <signal_name> (without init value) has a constant value of 0 in block <hierarchy_name>. This...

VHDL simulation failed with unexpected result

vhdl,fpga,hdl,spartan,xilinx-ise

Do you mean to do a data_read and data_write in this simulation? In RTL we can do a check like the following because we look many times (probably on an edge of clock): if start_data_read = '1' then However your testbench process does not loop. So instead of doing an...

FIFO error: can't find control signal - VHDL

vhdl,fpga,fifo

Trying to modify a single clock FIFO to become a clock domain crossing FIFO is no easy task. They are two very different beasts. I have attempted to draw a block diagram of the simplest possible clock domain crossing FIFO design. Excuse the crudity of my freehand drawing skills. My...

Arrays as buffer VHDL

What you are asking about here is a clock domain crossing FIFO, or CDC FIFO. Clock domain crossing FIFOs are surprisingly difficult to design. There are many pitfalls, and most of them cannot be checked by simulation. As for your arrays, you should use arrays of std_logic_vector, like in the...

Why this verilog assignment is wrong?

Note the bit widths of the signals in the expression M=(~S & X) | (S & Y); S is only one bit while X is 8 bits. The bitwise AND of the two will result in a one-bit result, which is not what you want. It's common in Verilog to...

VHDL Testbench code doesn't work for register

See the discussion of longest static prefix in the VHDL FAQ at: http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers For this reason, you need to re-write your instance as: Mgen : for i in 1 to N generate If_N : if i = N generate DR : SA_REGDR port map ( R=> R(10) ,EC=> EC(10), C=>...

What is wrong in this verilog code?

Some problems in the code are: for this situation is best with non-blocking assign. Explication 12 you are reassigning LEDR and LEDG with the case(SW[2]) statement You are toggling the values of LEDG and LEDR on each posedge(CLOCK_50). this is the reason why you see low intensity in leds. tips:...

Snake game using FPGA in VHDL

First of all, I recommend you split your display and your position update functionality into separate processes to make things clearer. You seem to already have mostly everything you need for your display process, except that, as Paebbels mentions in his comment, this should be a synchronous (i.e. clocked) process....

How to get rid of scale factor from CORDIC

math,vhdl,fpga,rtl,cordic

Each step in the CORDIC algorithm add a scaling of cos(arctan(2^-i)) (or 1/sqrt(1+2^-2i)), so for a 4 steps CORDIC, the total scaling is: cos(arctan(2^-0))*cos(arctan(2^-1))*cos(arctan(2^-2))*cos(arctan(2^-3)) = 0.60883 If you add more iterations, it gets to 0.607252935 and some. As to what to do with that factor, it's up to you and...

Error (10028): Can't resolve multiple constant drivers for net “sda” at I2C_com.vhd(185)

vhdl,fpga,quartus-ii

A signal for synthesis can be driven from only one process or one continuous assign; for simulation multiple drivers are possible using resolved signals like std_logic. The scl and sda are driven both from the i2c_clock process and the continuous assign in the end of the file. The start_clk and...

Errors in std_logic vector increment

You've got a lot of problems here. Your counter/state update logic is not synchronized to a clock (it's outside the IF clk'event) You are using signals as if they were variables. Your expressions are sensitive to variables not in the sensitivity list. Your case statement outputs sometimes the current state...

How to get a rgb picture into FPGA most efficiently, using verilog

image,verilog,fpga,vga,quartus-ii

Based on your compilation report, I'd recommend you using a block ROM (or RAM) memory, instead of registers to store your image. At this moment you're using distributed RAM, i.e. the memory that is available inside a each small logic blocks of FPGA. This makes distributed RAM, ideal for small...

Signal current cannot be synthesized, bad synchronous description

include,fpga,system-verilog,synthesis,rtl

The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware. In the case of your code, you have: if(A'event and A='1') then current <= nxt; end if; if(A'event and A='0') then current <= nxt; end if; -- etc...

Verilog Synthesis Error : “Expecting Endmodule”, when using `include directive

You're missing some ;s after the struct member declarations. Change it to: typedef struct { logic[2:0] three_bits; logic[1:0] two_bits; } t_five_bits; ...

Quartus Programmer II TCL flash *.pof file

tcl,fpga,quartus-ii

If you just want a command-line utility you can run quartus_pgm like this: quartus_pgm -z --mode=JTAG --operation="p;/path/to/[email protected]" where @2 indicates the device in the JTAG chain to program. You might also be interested in quartus_jli which writes JAM files. For full details look at the Quartus II Scripting Reference Manual....

What is the Intel Strata Flash Memory on Spartan-3E Starter Kit?

flash,intel,fpga,spartan

Flash can always be used to put static assets for your application, including microblaze program, configuration options, image, sound, etc. Most importantly, the fpga bitstream must resides on flash. All current xilinx fpgas are SRAM based and loose their content at poweroff. You need a non-volatile flash to store the...

VHDL short form to trigger actions on raising edges

You can write a rising or falling edge detection in two lines: a simple D-FF to register the old signal a comparison for the rising edge Example code: signal MMCM_Locked : STD_LOGIC; signal MMCM_Locked_d : STD_LOGIC := '0'; signal MMCM_Locked_re : STD_LOGIC; -- detect rising edge on CMB locked signals...

If statement using vhdl-counter

if-statement,vhdl,fpga

Notice your missing an port with mode in for inc_dec. As mentioned in the comment your if statement isn't a concurrent statement and needs to go in a process. Your increments and decrements for r_next aren't correct for VHDL. The pause shouldn't be asynchronous It infers a latch following the...

How to solve these warnings? | VHDL Programming

warnings,vhdl,fpga,xilinx

Complaining about dead/unused code WARNING:Xst:646 Signal <thirdaddress> is assigned but never used. Signal <secondaddress> is assigned but never used. Signal <firstaddress> is assigned but never used. This means these three signals are unused in your design. If you don't plan to use them in future, you can remove them ->...

vhdl-ultrasonic sensor(hc-sr04)

vhdl,sensor,fpga

Problem solved, code is working. I was giving 3.3V to sensor as Vcc, then I realized that I should give 5v. It worked. Thank you for everyone.

2's compliment input and using vhdl library for signed input

Your addition expression in adder1 is invalid because you're trying to index element "8" when the range of a1 and a2 is 7 downto 0. Assuming thet you're trying to sign extend it would look something more like this: q <=(a1(7)&a1 + a2(7)&a2); The "+" operator has higher precedence than...

Signal led cannot be synthesized, bad synchronous description?

The error message appears to be complaining that you are using the output of the cnt counter as a clock. Instead you could use it as a toggle enable and clk as the clock: --process (clock, btn) process (clk, btn) begin -- if btn = '0' then if btn =...

Why do I need to turn off IO buffers for my partially reconfigured module in Xilinx PlanAhead 14.7?

fpga,xilinx

When you synthesize your top level design in Project Navigator you should enable the IO buffers so that your design can access the external ports, but your internal modules should not have them enabled. Normally, IO buffers are automatically turned off for internal modules, but in the case of partial...

verilog code containing adders

You are performing unsigned arithmetic, as noted the MSB is 0 not 1 (negative) as expected. You need to declare the inputs, outputs and variables used as signed, for automatic sign extension. module out( input clk, input signed [9:0] s189, input signed [9:0] s375, input signed [9:0] s050, input signed...

SPI interface works in simulation but not on actual hardware

Take a look at the synthesis and timing (STA) warnings, since these will indicate if the synthesis tool could not implement the design to match the RTL VHDL code. The edge condition by rising_edge(...) or falling_edge(...) should only be used on a single common clock signal, unless there is a...

Synthesizing a counter with an asynchronous edge-triggered reset

The "Connected to multiple drivers" error is not a race condition - values cannot be assigned to the same net in multiple always blocks. Additionally, remember that HDL is not executed sequentially - placing an assignment earlier in a file won't give it any higher priority. Instead, you'll need multiple...

Inbuilt Adders used in FPGA

For most cases you can't beat the dedicated adder resources found in FPGAs. They have enhanced carry logic that is significantly faster than what you can create in the configurable fabric. In certain cases you may be able to do better than the hardware adder support if you switch to...

VHDL integer range inclusive? Difference in FPGA vs. simulation

vhdl,fpga,modelsim,altera

This happens because the line ledCounter <= ledCounter + 1 happens before the comparaison. Even if ledCounter's value won't actually reach 25000001, since overridden by the following statements, at this point it is scheduled to reach it, causing the simulation error. You can solve it easily by moving the increment...

Creating large dual-port RAM in VHDL

memory,vhdl,ram,fpga

You need to look at exactly what type of RAM your parts support. One thing that is may be causing problems is the initialization of the RAM. Some technologies do not support reset on their RAMs. Some will as a pre-load during power up. signal RAM : RAM_type := (others...

Multiplication by power series summation with negative terms

vhdl,verilog,fpga,vlsi

In a 4 bit base 2 number can have these values: Base 2: Unsigned 4 bit integer, 2^3 2^2 2^1 2^0 8 4 2 1 If we have a 0111 it represents 7. If we were to multiply by this number using a shift add architecture it would take 3...

VHDL beginner - what's going wrong wrt to timing in this circuit?

Did your timing report indicate that you had a timing problem? It looks to me like you were just rolling through the segment values extremely fast. No matter how well you design for higher clock speeds, you're rotating cur_anode every clock cycle, and therefore your display will change accordingly. If...

Verilog pipeline

While your idea seems fine, it might be better to use an Finite State Machine [FSM] ( http://en.wikipedia.org/wiki/Finite-state_machine ). Pretty much this just means that instead of a counter, you would have a variable holding a series of states with more human readable names. Using this, you need only have...

Are renamed clocks synchronous?

math,signal-processing,vhdl,fpga,lookup-tables

A synthesizer will transform your design input into an internal netlist that represents the logic structure. This is typically done in two stages. First to a high level behavioral form that represents abstract operations and then to a technology mapped form that directly implements logic primitives of the target architecture....

Why dynamic power consumption is always zero?

vhdl,fpga,xilinx,xilinx-ise

As Brian indicated in his comment, the reason your original power estimate had no dynamic power consumption was that when the design was originally simulated, it was simulated in a static state. That is to say, no elements of your design were toggling. The reason no elements of your design...

UART RS-232 Transmitter

serial-port,vhdl,fpga

Guess you are missing if clk'event and clk = '1' then, or rising_edge(clk), at the out-most level of the tx_process. The tx_next process also looks weird; it actually does nothing as written now (apart from delta delay)....

FPGA: Divide range by fixed number using a look-up table

Subtract 62710 (not 62720, to make the first range the same size as the others.). Notice that 20=5*4 so divide by 4 (omit the two LSBs). You now have a much smaller range to fit into the LUT. Also subtract 3072 from each LUT entry. (You only need to set...

How do I read the status register of a Virtex 5 in a JTAG chain?

fpga,jtag,virtex

I've actually worked on this same device. If I'm correct, when you look at the JTAG chain in iMPACT, you should see 5 devices: two PROMs, a SystemAce, and a CPLD, followed by the Virtex 5 as the final item on the chain. Like this: PROM -> PROM -> SysAce...

how does inout parameters be implemented?

verilog,fpga,system-verilog,computer-architecture

For typical FPGA and ASIC devices, implementation of tristate capabilities are only available on the IO, like for example in an Altera Arria 10 FPGA: So for such devices, the internal RAMs are always implemented with dedicated input and output ports, thus not using any internal tristate capabilities. Even if...

If statement using vhdl

if-statement,vhdl,fpga,xilinx

As pointed out by Morten Zilmer, you need to terminate the if/else with an end if. Also there have been some missing semicolons. The code below should work. if (inc_dec='1') then if (r_reg=(M-1)) then r_next <= (others=>'0'); else r_reg+1; end if; elsif (inc_dec='0') then if (r_reg=(M-10)) then r_next <= to_unsigned(9,...

Why use multiple clocks of the same speed in an FPGA design?

vhdl,clock,fpga

There are many reasons to use multiple clocks of the exact same speed. So I will just state a few. However i don't have any deep knowledge of your example. Magic on FPGA. Like stated in the comments a FPGA is a highly complex device. Only the vendor knows exactly...

hardware implementation of Modulo m adder

Do not mix blocking and non-blocking assignments in the same always block. sum3e variable depends on sum3a and sum3b but at the same time sum3a and sum3b value is changing because of non-blocking assignments,This will results in logical errors.

How expensive is data type conversion vs. bit array manipulation in VHDL?

None of the type conversions cost. The different types are purely about expressing the design as clearly as possible - not only to other readers (or yourself, next year:-) but also to the compiler, letting it catch as many errors as possible (such as, this integer value is out of...

Process evaluated too many times