Porting ARM to thumb2 [closed]
assembly,arm,instruction-set,thumb,cortex-m
Ubuntu has a nice overview page on porting ARM to Thumb-2. See https://wiki.ubuntu.com/ARM/Thumb2PortingHowto.
xorl %eax - Instruction set architecture in IA-32
It's probably: xorl %ebx, %ebx This is a common idiom for zeroing a register on X86. This would correspond with i = 0 in the C code. If you are curious "but why ?" the short answer is that the xor instruction is shorter than the mov instruction. I am...
Matlab-Using a function to command a function generator
matlab,function,instruction-set
I guess there is no need for the 'VP' at the end of the offset definition. An offset is just a voltage, specifying Vpp or Vrms doesn't really make sense. Try: Offs_str = ['OFFS' num2str(Offs)]; For the amplitude, in the manual it seems that there is a space between 'AMPL'...
opcode of transfer from memory to register
mov dl,[1000h] ; -> 100010 11 oo 010 mmm disp Your opcode encoding mistakenly addresses the DX register. The correct encoding is 10001010b, 0001_0110b, 0000_0000b, 0001_0000b So the mod field is 00b and the r/m field is 110b...
How to get instruction sets info in Android code?
android,cpu,sse,neon,instruction-set
You can fetch that info from /proc/cpuinfo. Use this code: BufferedReader br = new BufferedReader(new FileReader(new File("/proc/cpuinfo"))); String line; StringBuilder cpuInfo = new StringBuilder(); while ((line = br.readLine()) != null) { sb.append(aLine + "\n"); } Log.i(TAG, "CPU info: " + sb.toString()); The output of this command will contain all those...
How to save a group of registers and restore them later?
assembly,arm,cpu-registers,instruction-set
The first operand of LDM/STM (r0 in your examples) is the base register. That register holds the address in memory where the values in the register list will be stored. So, for example, when you STMIB r0!,{r1-r3} with r0==0x9000 you'll store the value of r1 at address 0x9004, r2 at...
g++ dumped assembly output doesn't work
c++,assembly,syscall,instruction-set
There are two things you're doing wrong: Firstly, you're the 64-bit syscall instruction, but initialize only the %e part of the registers. Secondly, this: movl -4(%rbp), %esi loads the value that is at -4(%rbp) (the 6 you just calculated) into %esi, when sys_write expects the memory address of that value...
Indirect/Indexed Addressing Mode
Not sure which architecture you're discussing so I'll just explain generically as best I can (based on experience wtih more concrete architectures, and investigative analysis of the stuff shown in the graphic you posted). Immediate mode means use the immediate value, so something like load r2, #800 would put the...
8 Register Machine with 4 2-operand instructions in 8-bit format
instruction-set,microprocessors
It's basically asking whether you can encode any of four different instructions, each with two register operands, into 8 bits (per instruction). The answer would be yes. Simply count the number of possible operations: 4 instructions * 8 possible first registers * 8 possible second registers = 256; you can...
Pipeline refill cycles for instructions in arm
assembly,arm,pipeline,instruction-set
The answer is right there in the question: between 1 and 3 cycles depending on things. Even on something as relatively simple as Cortex-M4 there are enough factors that it's not necessarily possible (or useful) to specify some hard-and-fast rule. However, that's not to say we can't do a bit...
Instruction Encoding relating to MARIE Assembly language
assembly,encoding,instruction-set,marie
You got the k=7 part correct. That of course provides space for 2^7=128 opcodes. As for the n, you need to consider how much memory you have to address. This is given as 128x2^20 words, which is 2^27, so you need at least n=27. The total instruction size is then...
How do I enable SSE for my freestanding bootable code?
If you're running an ancient or custom OS that doesn't support saving XMM regs on context switches, it won't have set the SSE-enabling bits in the machine control registers. In that case all instructions that touch xmm regs will fault. Took me a sec to find, but http://wiki.osdev.org/SSE explains how...
ARM v7-M Instruction Set Decoding Function
compiler-construction,arm,instruction-set,objdump
Yes, it's called a disassembler. Put the op code in an assembly file, build it, and then disassemble it. $ cat in.s .syntax unified .align 2 .code 16 .globl _foo .thumb_func _foo _foo: .short 0x4615 .long 0x43e0e92d $ clang -arch armv7m -c in.s $ otool -arch armv7m -tv in.o in.o:...