Does it make sense to optimize data hazards if a processor supports out-of-order execution?
optimization,data,dependencies,processor
A processor that is capable of executing out-of-order is not necessarily capable of eliminating any data hazards. Simple out-of-order execution implementations do not include register renaming and therefore WAW and WAR hazards will cause pipeline stalls. However, most modern OoOE processors implement register renaming thereby eliminating WAW and WAR hazards,...
Processor usage when using byte and short data types in Java
In order to do computation (like x+y), processor need to load both x and y in registers (depends on architecture, but at least on of x or y should be in registers). Registers have size of 32 or 64 bits (at least on platforms where Java can be used). So,...
Pointers and cache utilisation
c++,c,pointers,caching,processor
The exact answer is platform specific, but generally speaking, three things cause data in external memory to be loaded into the processor cache. The most obvious is an actual instruction that accesses the memory in the ordinary way. If that memory address is not resident in processor cache, the processor...
How to get cpu number in android and windows phone
android,windows-phone-8,processor
For getting CPU count in android use this: android_getCpuCount() from cpufeatures NDK library works correctly....
Apache Camel - Filname to process
I think you are looking for something like this: <from uri="ftp://ftp.x.com?username=x&password=x&binary=true&stepwise=false&delay=20000" /> <to uri="file://{{download_folder}}?fileName=${date:file:yyyyMMdd}_${file:name}&keepLastModified=true" /> <setBody><simple>${header.CamelFileNameProduced}</simple></setBody> <to uri="jms:queue:File.Process" /> ...
What is the better number of threads running simultaneous for specific processor?
I'm creating 160 threads simultaneous, so each core of my processor will process about ~20 threads, is it correct? Not quite. Each core can only process a single thread at a time. When the OS decides the thread had enough of the spotlight, it will switch it out for...
Xtensa instruction: L32R - which addres is loaded?
memory,assembly,embedded,processor
The Xtensa Instruction Set Architecture Reference Manual manual states on page 382 that for l32r the address is calculated as follows: L32R forms a virtual address by adding the 16-bit one-extended constant value encoded in the instruction word shifted left by two to the address of the L32R plus three...
Error trying to read the IVT in windows 7 64 bits
c,windows,assembly,intel,processor
NO you cannot do that on Windows without writing a kernel mode driver because you're running in long mode (the 64bit extension of protected mode). What you are asking to do is impossible in user mode From the linked blog post from Raymond Chen: Windows NT didn't have a lot...
Processor Multi-threading
multithreading,operating-system,processor
'If a program or application does not contain any threads' ..it can do nothing because it has no execution. All processes that are not in the state of being terminated have at least one thread - usually the one created by the loader to run code at the process...
AT91SAM7X-EK Evaluation Board [closed]
c,linux,embedded,arm,processor
The board is supplied "bare-metal" - no code, no OS. You will not be able to run Linux on an AT91SAM7X-EK - it has insufficient memory resources and rins at 30MHz tops (and has no MMU). You need a hardware JTAG or DBGU interface device and a tool-chain that will...
Bits change when passing wire bus to module
module,simulation,verilog,processor
You are not telling Verilog that the instruction is a binary number, so it is interpreting it as decimal. You need this: instruction = 32'b00100000000010000000000000000001; #100 //add $8, $8, $8 instruction = 32'b00000001000010000100000000100000; Additionally, you should not be putting assign statements inside an always block. If you want these to...
How to multi-thread a brute force java password program
java,multithreading,passwords,processor
This is not a parallel processing solution but a much more optimised brute force approach. You can consider changing the Iterator to a Spliterator. If time permits I will possibly give a Spliterator approach in a following post. package pwcracker; import java.util.Iterator; import java.util.Scanner; public class pwcracker { public static...
Application development on various devices
architecture,software-engineering,software-design,processor
It's a quite broad question. Without any technology it can be hard. It would be nice to know which programming languages are supported. If you know this, you could already start. Make all O.S. calls in a separate library so you can later connect them to the known O.S. However,...
Is there any way to set processor affinity of a powershell script before execution?
powershell,powershell-v2.0,processor,affinity
This seems to work for me, but I haven't tested it. It seems to update what Task Manager sees, however. $thisProcess = [System.Diagnostics.Process]::GetCurrentProcess(); $thisProcess.ProcessorAffinity = 0x1; ProcessorAffinity is a bitmask, so 0x1 is core 1, 0x2 is core 2, 0x4 is core 3, 0x8 is core 4, and so on....
How to create Custom Paperclip Processor to retrive image dimensions Rails 4
ruby-on-rails,ruby,paperclip,dimensions,processor
I reproduced your case and I believe the cause is the typo here: has_attached_file :avatar, processors: [:custom], :style => {:original => {}} It should be :styles instead of :style. Without a :styles option, paperclip does not do any post-processing and ignores your :processors. Also, here is a very simple implementation...
Linux Bash Command - Displaying Processor Speed - Specific Lines
linux,performance,bash,cpu,processor
You can do this using a regex. grep -P 'M?Hz' /proc/cpuinfo (I assume you made a a typo and meant Hz instead of HZ.) grep is a tool that reads from the input channel (or file if specified) and returns all lines that match a specific regex (regular expression). In...
How is arctan implemented?
algorithm,floating-point,processor,bits
Trigonometric functions do have pretty ugly implementations that are hacky and do lots of bit fiddling. I think it will be pretty hard to find someone here that is able to explain an algorithm that is actually used. Here is an atan2 implementation: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/ieee754/dbl-64/e_atan2.c;h=a287ca6656b210c77367eec3c46d72f18476d61d;hb=HEAD Edit: Actually I found this one:...
NodeJS: understanding nonblocking / event queue / single thread
javascript,node.js,processor,single-threaded
Threads and I/O have to do with operating system implementation and services, not CPU architecture. Operations that involve input/output devices of any kind — mass storage, networks, serial ports, etc. — are structured as requests from the CPU to an external device that, by one of several possible mechanisms, are...
Are cache-line-ping-pong and false sharing the same?
caching,multicore,computer-architecture,processor,false-sharing
Summary: False sharing and cache-line ping-ponging are related but not the same thing. False sharing can cause cache-line ping-ponging, but it is not the only possible cause since cache-line ping-ponging can also be caused by true sharing. Details: False sharing False sharing occurs when different threads have data that is...
Working of a kernel [closed]
kernel,cpu,scheduling,processor,opcode
I have a vague idea about "kernel" of an operating system. In a nutshell here is what I know There is an userspace and a kernelspace. Yes, these are generally enforced by the CPU. Protection "rings" limit which CPU instructions you can execute in user-mode (Ring 3 on x86),...
Is the processorid per core?
You will need to test this on your system as it depends on the type of CPU you have. It's likely to be one entry per logical (hyper-threaded) processor. Here is what msdn says On a multiprocessor computer, one instance of the Win32_Processor class exists for each processor. To determine...
Simulating 32 bit processor register - Compiler enough or 32 bit OS required?
gcc,operating-system,32-bit,processor
It depends on what you mean by "simulate a 32 bit register" a 64 bit register "simulates" a 32 bit register if you ignore the upper 32 bits.
C and inline asm bug
c,linux,pointers,assembly,processor
As mentioned by Carl Norum since you're asm statement doesn't fully describe its effect on the machine state likely what's happening is that you're clobbering a register GCC is using to store some value. Like say the Proc pointer. The solution is to define all the inputs and outputs of...
How many words can be in the address space?
64bit,cpu,memory-address,computer-architecture,processor
Thanks to aruisdante's comment, I was able to figure this out. Basically 64 bit addresses means there are 2 ^ 64 total addresses. Because byte addressable memory is used here, each address will store one byte. This means that in total, in the address space, 2 ^ 64 bytes can...