Verilog module instantiation
Looking over the code you posted in your comment, the issue is from instantiating your module inside your always @(posedge clk) block on line 70. You never instantiate modules inside of procedural blocks (always, initial, etc). As Verilog is a Hardware Descriptive Language, you have to be in the mindset...
LATCH Primitive disables outputs?
when WIN => deal <= '0'; dealTo <= '0'; dealToCardSlot <= "00"; if(playerWins) then greenLeds <= (others => '1'); elsif(dealerWins) then redLeds <= (others => '1'); else greenLeds <= (others => '0'); redLeds <= (others => '0'); end if; You do not assign redLeds if playerWins is false and...
Can signals be used instead of hard coding values multiple times?
I've read that signal assignments don't take place immediately. This is true, but I think you miss an important point, which is to know when they take place. Signals are updated when the process that generates them encounter a wait statement, or end (since there is an implicit wait...
VHDL: Trouble combining entities (components)
First, you have assigned the output of your AND gate to wire2, but wire2 is floating. You should either assign it to your ouput like this out_d <= wire2; OR remove wire2 from your internal signals and assign your output directly. and1 : AND_LOGIC port map(in_c, wire1, out_d); Second, your...
Edit top verilog component generated by Qsys
Ok, I found the solution. In fact, I selected design.qsys as «top-level». Doing this regenerate all HDL code. To avoid this, adding design.qip is a prefered way. This file can be found under the directory : design/synthesis/design.qip
VHDL: Why is output delayed so much?
The easiest thing to do would be to move the assignment out_C <= next_output; outside the process (make it a concurrent signal assignment). You could also make next_output a variable declared in the process and leave the signal assignment where it is. The delay happens because signal assignments don't take...