Why is this Shift Register not loading properly in VHDL?
Your simulation shows that your S input is always high. The way you have your conditions setup, this means that the last elsif statement will not execute because S has priority over W. If you want your write to have priority over your shift operation, you should switch your conditions...
4-bit Shift register with flip flop
FF1: flipflop port map(Sin,Clock,Enable, Q(3)); This is good, it does exactly what your diagram ask. FF2: flipflop port map(Sin,Clock,Enable, Q(2)); This is not good. This connects the input D of FF2 to Sin, while the diagram connects it to Q(3). You could try doing something like: FF2: flipflop port map(Q(3),Clock,Enable,...
Galois LFSR - how to specify the output bit number
If you need bit k (k = 0 ..15), you can do the following: return (lfsr >> k) & 1; This shifts the register kbit positions to the right and masks the least significant bit....