Dynamic Coverpoints in Coverage Systemverilog
system-verilog,function-coverage,questasim
What you are asking for cannot be done, nor does it make any sense. See https://verificationacademy.com/forums/coverage/how-get-values-different-bins-coverpoint
About the latches generated by “case” syntax
The clean and easy solution here is to assign a default value Carryout at the beginning of the always_comb block. The last assignment will win, so any branch that does not assign a value to Carryout will get the default value. A simple example of how the last assignment wins...
How to pass a class between two modules?
A variable of any type can be an input or output port. You might have to write for your compiler input var foo foo_inst, But it would be better to use a ref when a port is really a handle. module mod_A(ref foo foo_inst, ref event trig); Note that you...
How to overloading an operator in SystemVerilog
operator-overloading,system-verilog
I don't think any tool supports this construct.
About struct in system-verilog?
Functions declared inside structs are not supported as of IEEE Std 1800-2012. Looking over the syntax for structure declaration, a struct_union_member is a data_type_or_void and a function is not data_type. § 7.2 Structures data_type ::= // from A.2.2.1 ... | struct_union [ packed [ signing ] ] { struct_union_member {...
Interconnecting modules in combinational circuit, Verilog or SystemVerilog
A new answer based on the edited question. The answer will work through my process, understanding the problem and refining, otherwise the generates used will be pretty difficult to understand. Skip to the end to see the generate syntax. First an example of the desired connectivity from the given diagram....
Combinational logic “IF” and “assign” statement in systemverilog
I believe the issue is with your order of operation. always_comb blocks execute procedurally, top to bottom. In simulation, Z is updated first with the existing value of Result (from the previous time the always block was executed). The Result is updated and Z is not re-evaluated. Result is not...
Why is typedef can not be used in local in systemveriliog?
For your first question "why typedef cannot be used locally?" Typedef can be used inside any SystemVerilog module and can be accessed/initialized based on our needs. Refer Section 6.18 User-defined types of SV LRM IEEE 1800 - 2012 Here is one example which uses typedef inside the module struct {...
How to use throughout operator in systemverilog assertions
You're correct in wanting to use the throughout operator for your assertion, but the code you wrote has some problems. Let's look at it piece by piece. Whenever I write an assertion I pay attention to the natural language description of what I want to check. In your case, we...
wait($time >1000); cannot work in system-verilog?
This seems to be a gray area in the standard. In section 9.4 Procedural timing controls of the IEEE Std 1800-2012 Standard, it's mentioned that event control can be either implicit (changed of nets or variables) or explicit (fields of type event). $time is a system function, not a variable....
Systemverilog: Simulation error when passing structs as module input\outputs
struct,system-verilog,dpi,questasim
SystemVerilog has strong typing rules for user defined types. A typed declared in one scope is not the same as a type declared in another scope, even if it has the same name and same internal layout. A user defined type is only compatible with itself. Define your types in...
'this' equivalent for SystemVerilog interfaces
There is a proposal to use an upward reference in place of this, but nothing has been finalized yet.
Array of systemverilog interfaces with different inputs
arrays,interface,system-verilog
I would avoid using assign statements, especially with hierarchical references; it makes the code much more difficult to read and maintain. You could have just done reg clk[`NUM_INTERFACES]; x_if x_IF[`NUM_INTERFACES](clk); A feature with arrays of instances is that if the width of a signal being connected to a port is...
Systemverilog doesn't allow variable declarations after call to super.foo()?
It is illegal syntax. All variables in a task or function must be declared before any operation. See IEEE Std 1800-2012 § 13 Tasks and functions (subroutines) Legal syntax is: function void foo(); bit test_one; bit test_two; super.foo(); endfunction The only exception is a begin-end block in which case the...
How does 'event' works? [on hold]
I think you may be confused about why the events are printed multiple times? Have a look at line5: event done = ack; Now ack and done are synonymous with each other, whenever one event is triggered the other is as well, since each is triggered once you get 4...
Event on logic value change
Try @(!a). By putting it through a Boolean expression, it loses its strength. The only thing you loose is x->z transitions. (your solution would not catch that either). If you need that, you had better explain better what you are trying to accomplish, where might be an entirely different approach...
Best way to check if variable is part of collection of enums?
There are a couple of ways you could do this. If you can depend on the encoding, then you can define your collection with a wildcard and use the wildcard equality operator or inside operator let COMP_STATES = 3'b00?; // or parameter COMP_STATES = 3'b00?; let RUN_STATES = 3'b01?; //...
connecting VHDL port to system verilog interface definition in UVM
vhdl,system-verilog,uvm,cadence
First, your problem is that you're not defining the loop_array_ty correctly. It should be typedef raccu_loop_reg_ty loop_array_ty[MAX_NO_OF_RACCU_LOOPS-1:0]. I would suggest 2 things here: First, try removing the packed qualifier from the struct definition. Connecting SV structs to VHDL records is something that is only available in newer Incisive versions. Make...
how to use 2 Dimensional array in Verilog
arrays,multidimensional-array,verilog,system-verilog
Your code causes index_C and index_R to overflow, and needs a multiplication operation which may be expensive if this desription is meant to be synthesized. simple_State has 11 rows and 11 columns, so a 4 bit for row index and column index is enough. Just do as you would do...
Can I access delayed value in SystemVerilog assertion
fpga,verification,system-verilog,assertion
You can use the $past(...) system task. Using $past(rdaddress) will return the value of rdaddress that was sampled in the previous cycle. You can specify how many cycle in the past to go with the second argument. In your case, calling $past(rdaddress, 2) will return the value of rdaddress 2...
variable-sized parameter array in verilog
verilog,system-verilog,modelsim
Turns out this is a modelsim bug. This input yields different results on two different modelsim versions: parameter NUM_DEST = 4, parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1] modelsim 10.3d = correct modelsim 10.1e = wrong To fix it in all cases, we can initialize the array with the parametrized number of inputs...
8 bit wide, 2-to-1 multiplexer verilog module
While there are multiple ways to do this, I suggest make a wrapper module containing the board i/o as inputs and outputs and instantiate your MUX inside of it: module top(input [17:0] SW, output [15:0] LEDR, output [7:0] LEDG); example ex(.M(LEDG), .s(SW[17]), .X(SW[7:0]), .Y(SW[15:8])); assign LEDR[7:0] = X; assign LEDR[15:8]...
Disabling a scoreboard from a sequence using UVM
You can create one dedicated uvm_object to do that. For example: class feature_options extends uvm_object; bit sb_enable=0; // ... endclass Instantiate it in your top-level testbench, and then put it in uvm_config_db: // in your top-level testbench: feature_options f_opt; initial begin f_opt = new("f_opt"); uvm_config_db#(feature_options)::set(uvm_root::get(), "*", "FEATURE_OPTIONS", f_opt); end and...
What is advantage of structure?
Structure in SystemVerilog is more or less similar to structure usage in C-language, structure is a collection of different data types, variables or constants under single name. For more details you can always refer SystemVerilog LRM IEEE Std 1800-2012 ♦ 7.2 Structures I will here explain the more common usage...
Randomization of a class object inside a class in SystemVerilog
The == operator when applied to object doesn't do what you think it does. It only compares the handles. The solver is failing because it sees that o1.o2 and o2_local are different objects and thus aren't "equal". If o2_local isn't supposed to be changed by the randomization then you can...
choose interface parameters in module declaration
The current SystemVerilog syntax BNF does not allow you to specify a parameter specialization of an interface port. It will acquire the parameterization from the instance that get connected to the port module foo(Foo in, output logic [in.WIDTH-1:0] out); assign out = in.data; endmodule interface Foo #( parameter WIDTH=8 );...
verilog code to convert binary input into residue number system
In [email protected](posedge clk) use non-blocking assignments (<=). The way you have defined initial values is not typical. Either use and initial block or a reset. initial begin dout0=9'd0; dout1=9'd0; dout2=9'd0; dout3=9'd0; dout4=9'd0; dout5=9'd0; dout6=9'd0; dout7=9'd0; mod30=3'd0; mod31=3'd0; mod32=3'd0; mod33=3'd0; mod34=3'd0; mod35=3'd0; mod36=3'd0; mod37=3'd0; ... end Or [email protected](posedge clk, negedge rst_n)...
hardware implementation of Modulo m adder
verilog,fpga,system-verilog,computer-architecture
Do not mix blocking and non-blocking assignments in the same always block. sum3e variable depends on sum3a and sum3b but at the same time sum3a and sum3b value is changing because of non-blocking assignments,This will results in logical errors.
Randomization Order in Systemverilog
The problem SystemVerilog does not allow you to use an expression with a random variable as an index to an array. You need to put your constraint in terms of a foreach loop. Also - a solve before directive does not change the solution space, just the distribution of values...
Inferring latches in Verilog/SystemVerilog
memory,verilog,system-verilog,quartus-ii
The type of assignment used in a combinatorial block will not effect synthesis. The use of non-blocking (<=) may result in RTL (pre-synthesis) to gates (post-synthesis) simulator mismatches. The same is true for sensitivity lists, synthesis will give the behaviour of auto generated or complete list. In a clocked process...
importing VHDL packages to SV from libraries other than WORK
vhdl,system-verilog,assertions
The problem seems to be indeed vendor-specific, as @toolic mentioned. For some reasons it works when I write the record elements in the lower case. The rest (signals, modules) I wrote in the same case as it was in VHDL, and it worked. Only the record elements caused problems until...
How to write pulse width systemverilog assertion when width is configurable
You need to use a local variable, see IEEE Std 1800-2012 § 16.10 Local variables Here is a simple example: property p_PropA; int count; @(posedge clk) ($rose(active),count=config) |-> (active,count--)[*] ##1 (~active && count==0); endproperty ...
Verilog - Compile time calculations
parameters,system-verilog,synthesis
The main problem is $floor is a function that returns value with a real type. Since you did not explicitly provide data types for your parameters, they are implicitly defined with the type of the default initialization or the type of any expression they ore overridden with. So when you...
Verilog syntax errors
You have an error in replication operator, i.e. 32{MPLR[1]}. The correct syntax for this operator looks like following: {n{m}} //Replicate value m, n times As you can see, there are two {} brackets needed. In your code it would be {32{MPLR[1]}} and {32{MPLR[0]}}....
Access parent class variables from nested class
Don't make the confusion of thinking that just because you define class rand_x inside the class random_messages, it automatically means that an object of the nested class gets instantiated inside an object of the wrapper class. Declaring a nested class only changes the scope where it is defined. In your...
verilog $readmemh takes too much time for 50x50 pixel rgb image
verilog,fpga,system-verilog,quartus-ii
First, some background: It's likely you're getting "Timing requirements not met" because of the size of the image - 50x50x8x3 is a fair number of storage bits, moreso if it's attempting to store them into logic instead of on-chip RAM. A 640x480 image is 900 kB, so only the biggest...
What is the meaning of this code statement in verilog?
When `vend_a_drink is present it is replaced with {D,dispense,collect} = {IDLE, 2'b11} during pre-compilation.
How to check signal drive strength?
Drive strength is shown using the special %v character. $display("a is %v" a); The values shown by %v Strength Value %v supply 7 Su strong 6 St pull 5 Pu large 4 La weak 3 We medium 2 Me small 1 Sm highz 0 HiZ Source. To check a value...
My verilog VGA driver causes the screen to flicker (Basys2)
verilog,fpga,system-verilog,xilinx,vga
I'm posting this as an answer because I cannot put a photo in a comment. Is this what your design looks like? My only guess ATM is that you might have misplaced some ports during instantiation of vga_driver and/or map_generator (if you used the old style instantiation). Nevertheless, I'm going...
Assertion to verify a glitch in a signal
You're mixing up stuff here. By writing a clocked assertion on signal a you're verifying that it is a synchronous signal that has a specific behavior. Synchronous signals can glitch all they want in between clock edges, because they never get sampled there. This is exactly the reason why we...
verilog code containing adders
You are performing unsigned arithmetic, as noted the MSB is 0 not 1 (negative) as expected. You need to declare the inputs, outputs and variables used as signed, for automatic sign extension. module out( input clk, input signed [9:0] s189, input signed [9:0] s375, input signed [9:0] s050, input signed...
How to access randomized sequence_item from another sequence?
If you want to synchronize traffic across multiple sequences, your best bet is using a virtual sequence: class virtual_seq extend uvm_sequence; sequence_a seq_a; sequence_b seq_b; `uvm_declare_p_sequencer(virtual_sequencer) task body(); // create sequence A // ... // start sequence A on appropriate sequencer fork seq_a.start(p_sequencer.seqr_a); join_none // wait until seq_a's item finishes...
Issue with reading bus signal. Compare to my Modelsim DE 10.2c and 10.4. EDAplayground Modelsim 10.1d has different result
I cannot find an explication for the race condition, but I have found two workarounds that will work with all versions. One approach is to use a while-loop with the clock as the blocking event and the net as the compare condition. while(bus.MONCLK.FRAMEn!=1'b0) @(bus.MONCLK); The other approach is to use...
left-justified text for pli call
Find another solution. First create a parameter for the format string. Use a parameter to the format evaluational only happens at compile/elaboration time, it will be static during simulation. parameter FORMAT_LJUSTIFY = $sformatf("%%-%0ds",CHAR_NUM/8); So if CHAR_NUM is 640, then FORMAT_LJUSTIFY will be "%-80s", meaning the last 80 characters will be...
Tick-including a header file inside package in systemverilog
I recreated your scenario on EDAplayground. I didn't get any errors. A function is intended to be evaluated during simulation. Some simulators support evaluating function during compile/elaboration, but it doesn't appear to be a requirement. SystemVerilog also has let, which is more appropriate for for compile time evaluation (it supports...
How to use UVM factory's set_inst_override_by_name to override sequence item
Where you create your packet, you'll need to to specify the full path to the corresponding call to create(..): packet = a_packet::type_id::create("packet", , get_full_name()); If you were using the uvm_do macro, you'll have to change to using the explicit sequence API: packet = a_packet::type_id::create("packet", , get_full_name()); start_item(packet); // ... randomize...
Verilog generate statement : conditional port connections
For the port connections from a sequence of 0,1,2,3 you need to generate the following sequence 3,0,1,2. The transfer function is +3 modulus 4. genvar i; generate for(i=0; i<=3; i=i+1) begin : mymodules mymodule m (.a(myreg[i]), .b(myreg[(i+3)%4]), .c(i[1:0]), .d(???)); end endgenerate Also note that you want your loop to run...
Passing “type” argument to functions
oop,verilog,system-verilog,uvm
A colleague of mine suggested this solution similar to what Dave suggested. virtual class eclass_creator #( type T = bclass ); static function T create(int k) ; create = new(k) ; endfunction endclass This allows to create a scoped constructor. class bclass; int i; function new(int k); i=k; endfunction virtual...
Syntax for looping through lower dimension of multidimensional associative array in a constraint
When using a foreach on an double associative array, you need to include all the significant indexes. Otherwise the loop can not determine how to how many times to loop for i. The simulator also needs to handle for the case that slba_previous[nsid] doesn't exist And there for have no...
How to add vertical alignment feature to a major-mode for Emacs
emacs,elisp,vertical-alignment,system-verilog
According to @homeless reply, I did modification: Use narrow-to-region to avoid region boundary changes. (defun align-decl-vertically () "Align verilog declarations." (interactive) (save-excursion (save-restriction (narrow-to-region (region-beginning) (region-end)) ;; remove spaces around ":" (goto-char (point-min)) (while (re-search-forward "\\s-*:\\s-*" (point-max) t) (replace-match ":")) ;; align "[" (align-regexp (point-min) (point-max) "\\(\\s-*\\)\\[" -1 1 0)...
Driving two different sequence items in one interface
What you want to look at here is protocol layering. You need to have a sequencer for each protocol sending items downward to each lower layer. At the bottom you'd have your driver that actually drives the DUT signals. Each sequencer needs to run a translation sequence that converts from...
Code for 8 point DCT using shifters and adders
The warning messages are self descriptive and you are only dealing with four types: WARNING:Xst:646 - Signal <signal_name> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <signal_name> (without init value) has a constant value of 0 in block <hierarchy_name>. This...
Inbuilt Adders used in FPGA
For most cases you can't beat the dedicated adder resources found in FPGAs. They have enhanced carry logic that is significantly faster than what you can create in the configurable fabric. In certain cases you may be able to do better than the hardware adder support if you switch to...
verilog “~” operator in addition operation gives unwanted result
The operands of the add operator need to be extended to the size of left hand side (or the max width of the two operands depending on the context) before the addition is done. In this case mode_u2 needs to be extended to 32 bits. I wasn't able to find...
functional_coverage not showing proper result
system-verilog,uvm,function-coverage
Whether the coverage is cumulative over all runs depends on what you're analyzing. I'm guessing you're analyzing only one simulation, though. Your calculation is correct, the maximum coverage you could get per test is about 40% (basically 40% per each coverpoint, averaged together), but that's highly unlikely to reach. What...
How to match and delete an element from a queue?
queue.delete(int'(queue.find_first_index( x ) with ( x == obj_to_del ))); works for me. It would really help if you could provide complete self contained examples like the one below: module top; int queue[$] = {1,2,3,4,5}; let object_to_del = 3; initial begin queue.delete(int'(queue.find_first_index( x ) with ( x == object_to_del ))); $display("%p",...
how to search string inside another string in system verilog?
You can use the svlib library from Verilab that wraps the C functions we know and love in SystemVerilog functions. It provides its own Str class that can tell you if a string contains a certain substring: Str my_str = Str::create(a); if my_str.first("qwerty") $display("found it"); You can find svlib at...
How to check class randomized object result with its derived class constraint
You could copy the contents of pkt into a new packet of type good_packet and then check if the constraint holds. First, you'll need a function that can update the fields of a good_packet based on the fields of a random_packet: class random_packet extends uvm_sequence_item; // ... virtual function void...
Order of size specifiers in unpacked ports
arrays,verilog,system-verilog,hdl
In Verilog input logic a[10] logic is not allowed and will cause Single value range is not allowed in this mode of verilog error. You need to declare an array using range (i.e. [9:0]). On the other hand, in SystemVerilog you can declare an array using range or size (i.e....
error: cannot convert 'bool' to 'svLogic*' in assignment
c++,gcc,system-verilog,dpi,modelsim
Given that you had: vc_putScalar(mem_req_rdy, mm->req_cmd_ready()); I am guessing that mem_req_rdy is of pointer type svLogic* (since from the name of the function vc_putScalar, it seems that it intends to change the value held in mem_req_rdy). So you need to dereference the pointer as in the following statement: *mem_req_rdy =...
Parameterized function errors
verilog,system-verilog,hdl,modelsim
The issue is where you define localparam. Parameter definitions are not allowed inside tasks and functions, see IEEE Std 1800-2012 § 13.3 Tasks and § 13.4 Functions. This should be a compiling error. Move the definitions above the function definition and the runtime crash will go away. This will also...
Implementing UVM Agent in slave mode
What you want is also referred to as a reactive agent. Don't confuse it with a passive agent, which is an agent that only monitors signals, but doesn't drive them. What you would do in such an agent is just start an endless loop on the sequencer that drives slave...
How to initialize clocking block signals at reset
While it's illegal to assign nets from procedural code, it's legal to force values onto them. You can do the following: @(negedge vif.rst); force vif.opcode = 0; Bonus: IMO you shouldn't have opcode defined as a wire. The illegal combination of procedural and continuous driver warning is wrong. The SV...
What is the meaning of an object of the class inside it's class-endclass definition?
This is how the singleton pattern gets coded in SystemVerilog. The singleton pattern is an OOP technique that makes sure only one instance of a class type is ever constructed. The constructor as well as the object rp are declared local. The only way to retrieve an instance of a...
Generate Statement in verilog for multiple Blocks
Multiple divers means that you have multiple modules trying to set the value of Reg. As a side note I really would advise to use some thing else other than Reg as a signal name, not least because at the top level it is a wire. Thinking about your generate...
how to use function in systemverilog?
Given the code snippet, check_device is the name of the function you are defining. It would return a value of type device, which as you said is typedefed as an enum definition. In SystemVerilog, you can declare an explicit event and wait on that. The operator -> is used to...
Parameter passing in Systemverilog
From your code snippet: xxx_model is a parameterized module that takes a parameter of type string named inst_name. you are instantiating this module and ce_0 is the name of the instance. you are passing value {inst_name,".ce_0"} as the value of the parameter. In this context Systemverilog will interpret curly braces...
How to access the structures from testbench
Until and unless struct is of single direction there won't be any difficulty in connecting test-bench and DUT ports together Here at your test-bench code comment out reg declaration of structure members and use structure declaration //reg a.tag,a.valid; my_data a; and try to run your code, the corrected/working code can...
Updating a classes' variable in a constructor through pass by reference?
Qiu did point me to the issue with my code. My problem was that, whilst the variables were declared correctly on both ends, one of my constructors was written: function new(ref int num_items); where it should have rather been function new(ref int unsigned num_items); Thank you Qiu....
Concatenate arrays of bytes into one array
No need to use generates a standard for loop will do: reg [7:0] bank3[0 : 255]; reg [7:0] bank2[0 : 255]; reg [7:0] bank1[0 : 255]; reg [7:0] bank0[0 : 255]; reg [31:0] address_array[0:255]; integer i; always @* begin for (i=0;i<256;i=i+1) begin address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]}; end end In SystemVerilog: logic...
Verilog Synthesis Error : “Expecting Endmodule”, when using `include directive
include,fpga,system-verilog,synthesis,rtl
You're missing some ;s after the struct member declarations. Change it to: typedef struct { logic[2:0] three_bits; logic[1:0] two_bits; } t_five_bits; ...
System Verilog simulation versus execution
The Verilog languages are quite low level so when designing hardware for FPGA or ASIC we have combinatorial logic and sequential logic. Assertions in any tools are really for verification, the concept is to high level to be able to get the hardware you want. SystemVerilog is not just for...
Initializing arrays in Verilog
You can use an initial block as well. This is allowed in simulation and is synthesizable on some architectures (Xilinx FPGA and CPLD support register initialization) reg [9:0] count reg [9:0] Save_state [0: 1024]; integer i; initial begin count = 0; for (i=0;i<=1024;i=i+1) Save_state[i] = 0; end always @ (posedge...
How to update regmodel with writes going from RTL blocks
For the first case you have to pre-load your memory model with your ROM contents at the start of the simulation. There isn't any infrastructure to do this in uvm_memory (unfortunately), so you'll have to implement it yourself. For the second case, you have to use a more grey-box approach...
Why two exactly “wire” statement in systemverilog, one can be compiled and the other on can not?
In module IDEX you have: MUX_5 MUX_5 ( .y (y), //<-- y used .a (IFID_Instruction[15:11]), .b (IFID_Instruction[20:16]), .sel (RegDst) ); wire RegDst; wire [4:0]y; //<-- y declared In Verilog and SystemVerilog variables, wire and regs should be declared before they are used. If an unknown name is used it is...
How to connect a checker to an arbitrarily instance?
What you can use in this case is a bind. This makes it possible to instantiate your checker anywhere inside the hierarchy. First you need to make the overflow signal an input instead of relying on the hierarchical path: module CheckOverflow(input bit clk, input logic overflow); In your top level...
Does $stable in SystemVerilog Operate on Buses?
According to the spec, $stable operates on the entire expression. Whereas $rose and $fell operate on the LSB of the expression. From section 16.9.3 of IEEE 1800-2012: — $rose returns true if the LSB of the expression changed to 1 . Otherwise, it returns false. — $fell returns true if...
How factory is implemented inside UVM?
This DVcon paper Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification was written with the UVM factory in mind before it was publicly released. All the same principals apply.
Can I synthesize a parameterized function in systemverilog where structure is used as a parameter?
verilog,system-verilog,synthesis
According to http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf § 5.6.7 Parametrized task/function arguments using static classes, the class must be virtual and defined in the $unit declaration space. This means the class cannot be defined inside a package. It is a weird requirements, as the paper points out. Try moving the class out of the...
Drive different elements of a structure from different modules
The rules for structs are the same for integral bit vectors. You can drive independent selects of them depending on how they are declared as wires or variables. Wires can have multiple continuous drivers, and variables can have a single continuous driver, or multiple procedural assignment. Note that a port...
SystemVerilog: How to create an interface which is an array of a simpler interfaces?
arrays,interface,system-verilog
Part 1 : Declaring an array of interfaces Add parentheses to the end of the interface instantiation. According to IEEE Std 1800-2012, all instantiations of hierarchical instances need the parentheses for the port list even if the port list is blank. Some tools allow dropping the parentheses if the interfaces...
code for shift add unit
By not "get correct result", I'm assuming you mean the results are coming delayed. Try moving the z0,o0,p0 assignments into a combinational block: always @* begin z0 = j0-j7; o0 = (z0<<3)+z0; p0 = (z0<<4)+o0; end [email protected](posedge clk ) begin s089 <= (z0<<6)+p0; s075 <= (p0<<1)+p0; s050 <= (p0<<1); s018...
How to get source of a sampled bin in Coverage in QuestaSIM
system-verilog,function-coverage,questasim
Well I have found out the answer of the question, so here I am posting it. In QuestaSIM, while merging the coverage a flag can be used for the same purpose. vcover merge -testassociated This flag will keep an eye on each test's contribution to the coverage. So after merged...
system verilog assertion disable condition
There is no disable_iff keywords, it is disable iff (without the underscore). Properties can have local variables but the local variables cannot be defined inline with assert. Separate the property definition and the assertion instantiation. The clock sampling doesn't seem to be correct. @(posedge fast_clk, clk_1MHz) mean on rising fast_clk...
Format specifications for real numbers
Using %7 works for your values with 2 simulators I tried: module tb; real expected, actual; initial begin expected = 12.25; actual= 12.75; $display("expected= %7.2f, actual= %7.2f", expected, actual); expected= 4093.25; actual= 4094.75; $display("expected= %7.2f, actual= %7.2f", expected, actual); #5 $finish; end endmodule /* Output: expected= 12.25, actual= 12.75 expected=...
How to check that Verilog enum is valid?
You can also use $cast to check if it is valid, and copy at the same time. So instead of doing: cmd = my_cmd'(value_from_bus);, you can do this: if ($cast(cmd, value_from_bus)) $display("Valid: %s", cmd.name()); else $display("Invalid"); Example on EDA Playground...
Verilog assignments in a sequential always
Non-blocking assignments are used to prevent race conditions between multiple processes that write and read the same variable on the same clock edge. It just takes one process that writes, and another process that reads the same variable on the same clock edge to create that race. Your example does...
cross coverage of transition in functional coverage of sysem verilog
You don't need cross-coverage to do what you want. Simple transition coverage should be sufficient. You just have to say that you're interested in 2 transitions. Let's say you have an enum type defined like this: typedef enum { A, B, C } some_type_t; You can define double transition for...
Why is an always followed by assign?
There seems to be a common misunderstanding on how verilog types work, that is if a modules port is connected to a wire, which it has to be, then the port should be defined as a wire inside the module. So you often get : module example ( output wire...
'run' phase is ready to proceed to the 'extract' phase
I am not sure about what script your are talking about. But it looks like you do not quit vsim. Try quit in your do file.
Insert string or comment into vcd dump file
There is no standard system task to write a comment string into a vcd file although $comment is a vcd keyword for creating comment sections: From IEEE Std 1800-2012 LRM: $comment This is a single-line comment $end $comment This is a multiple-line comment $end I would experiment with $dumpoff, $dumpflush,...
Which region are continuous assignments and primitive instantiations with #0 scheduled
This is an easy one. Section 28.16 Gate and net delays of the 1800-2012 LRM as well as section 7.14 Gate and net delays of the 1364-2005 LRM both say For both gates and nets, the default delay shall be zero when no delay specification is given. So that means...
What is the benefit of automatic variables?
Traditionally, Verilog has been used for modelling hardware at RTL and at Gate level abstractions. Since both RTL and Gate level abstraction are static/fixed (non-dynamic), Verilog supported only static variables. So for example, any reg or wire in Verilog would be instantiated/mapped at the beginning of simulation and would remain...
Using Systemverilog static variable in class
You should use a configuration object that contains the variables X and Y. Then have the base class A construct the config object if it does not exist and then do set it for each instance of the agent. class A extends uvm_component; my_config_c myconfig; function void build_phase(uvm_phase phase); ......