How can I merge several Xilinx NGC netlists to an new netlist
vhdl,xilinx,synthesis,xilinx-ise,netlist
Internal debates on how easy it was to find the answer aside there's some cause for propagating the question and it's answer in Stackoverflow. The idea being Stackoverflow is a search resource before someone asks the same question again, striving to be a higher quality resource in general than found...
Xilinx syntax ERROR:HDLCompiler:806
Line 51 misspelled process on Line 50 (will collapse the next errors on Lines 54, 58) Line 63 Roll='1' should be Roll <= '1' (Will collapse errors lines 64, 65). Line 69: else Sp ='1'; Nextstate <= 4; should be else Sp <= '1'; Nextstate <= 4; Line 68: (not...
SPI interface works in simulation but not on actual hardware
Take a look at the synthesis and timing (STA) warnings, since these will indicate if the synthesis tool could not implement the design to match the RTL VHDL code. The edge condition by rising_edge(...) or falling_edge(...) should only be used on a single common clock signal, unless there is a...
Finding the last variable in __attribute__(section)
c,linker,cross-compiling,gnu,xilinx
You can use a linker script for that. Maybe you are already using one to specify the memory section attributes. So, just add: MEMORY_CACHEABLE : { BEGIN_MEMORY_CACHEABLE = .; *(MEMORY_CACHEABLE) END_MEMORY_CACHEABLE = .; } Then in the C code: extern char BEGIN_MEMORY_CACHEABLE, END_MEMORY_CACHEABLE; And use &BEGIN_MEMORY_CACHEABLE as a pointer to...
I get “cannot index into a non array” error although I have declared the variable 4 bits. Using Vivado to program NEXYS 4
You have declared count 4 bits with wire [3:0] count; but the error is about count1. As it is not declared it is being created as a 1 bit wire. Just add wire [3:0] count1; to the top level module Clock...
Windows CE: Mapping Physical memory in user mode
memory-management,arm,windows-ce,xilinx
After long struggle, I found the answer. DWORD GetVirtualAddress() { HANDLE hCurrentProcess; HANDLE hCallerProcess; DWORD pAddr; PHYSICAL_ADDRESS pa; hCurrentProcess = (HANDLE)GetCurrentProcess(); hCallerProcess = (HANDLE)GetDirectCallerProcessId(); pa.QuadPart = 0xe000a000; pGpioRegs = MmMapIoSpace(pa, sizeof(XILINX_GPIO_REGS), FALSE); if (!pGpioRegs) RETAILMSG(1, (L"Cannot map the gpio register.\r\n")); pAddr = (DWORD)VirtualAllocCopyEx(hCurrentProcess, hCallerProcess, pGpioRegs, PAGE_SIZE, PAGE_READWRITE | PAGE_NOCACHE); if...
Dynamic Arrray Size in VHDL
You can't do that in VHDL. What kind of hardware would be generated by your code? If you don't know, the synthesizer won't either. The way to do this kind of thing is to set N to the largest value you want to support, and use size in your logic...
What could cause an extra bit to be added to a result in a non-blocking assignment?
verilog,cpu-architecture,xilinx,risc
When you write (below) the Right hand side is an Integer (Decimal, base10), not binary (base2). Only use non-blocking when implying flip-flops. initial begin RW <= 0; MD <= 00; BS <= 00; PS <= 0; MW <= 0; FS <= 00000; MB <= 0; MA <= 0; CS <=...
VHDL Testbench code doesn't work for register
See the discussion of longest static prefix in the VHDL FAQ at: http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers For this reason, you need to re-write your instance as: Mgen : for i in 1 to N generate If_N : if i = N generate DR : SA_REGDR port map ( R=> R(10) ,EC=> EC(10), C=>...
Leon v3 ise-prog-prom error: impact:2070
This message is generated because your programmer cannot find any JTAG devices on the chain to program. It's not connected to the device you're trying to program. How to troubleshoot that specifically is hard to say, I would suggest for starters that you make sure the programmer is connected correctly...
HDLParsers:800 Type of “**” is incompatible with type of “**”
This answer is provided because the other 7 occurrences of ERROR:HDLParsers:800 on Stackoverflow don't involve literals assigned to integer types, and Morten thinks an actual answer to the question may be valuable. The closest matching question with an answer (See VHDL: Type of “variable” is incompatible with type of <=)...
Verilog asynch mem in Xilinx
I am assuming this is part of a clocked synchronous block, i.e. something like the following (it would not make much sense otherwise and you wrote "I need to do all the shifts within one clock cycle", which implies that this is part of a synchronous design): reg [MSB:0] a...
How do i connect my two modules?
You're missing declaration of alu in ralu, i.e.: alu myALU( .op1(op1), .op2(op2), .func(func), .out(out) ); ...
VHDL/PlanAhead Error: remains a black-box since it has no binding entity
I deleted and re-added design & simulation sources, which still left the black-box. I opened a new project and added the sources before the project was created and the simulation ran without a problem.
UHD Ubuntu 12.04 ZyBo ARMv7 32bit getting libboost-all-dev
installation,arm,ubuntu-12.04,embedded-linux,xilinx
libboost-all-dev is available for arm, but accessing it requires Linux knowledge: 1.Search “Update Manager” 2.Click “Settings” on bottom left 3.Click on “Ubuntu Software” tab on upper left. 4.check/select the box “Community-maintained free and open-source Software (Universe)” 5.click “close” on bottom right...
How 16 bit array needs 5 bit address (Xilinx Vivado HLS)?
hardware,xilinx,synthesis,digital-design
From the UG871, it seems that the size of the array is from 0 to 16 samples, hence you need 32 addresses to access all values (see Figure 69). I guess that the number N is somewhere limited to be less than 32 (or be exactly 16). This means that...
How to write input values at different clock cycles in test bench of v/hdl programing?
You want to implement a shift register to feed data in serially. In general you should use case statements only for control logic and not data flow. Treating the data vector as an addressable array is also possible but it synthesizes to a decoder which will become a timing problem...
2's compliment input and using vhdl library for signed input
Your addition expression in adder1 is invalid because you're trying to index element "8" when the range of a1 and a2 is 7 downto 0. Assuming thet you're trying to sign extend it would look something more like this: q <=(a1(7)&a1 + a2(7)&a2); The "+" operator has higher precedence than...
My verilog VGA driver causes the screen to flicker (Basys2)
verilog,fpga,system-verilog,xilinx,vga
I'm posting this as an answer because I cannot put a photo in a comment. Is this what your design looks like? My only guess ATM is that you might have misplaced some ports during instantiation of vga_driver and/or map_generator (if you used the old style instantiation). Nevertheless, I'm going...
how does inout parameters be implemented?
For typical FPGA and ASIC devices, implementation of tristate capabilities are only available on the IO, like for example in an Altera Arria 10 FPGA: So for such devices, the internal RAMs are always implemented with dedicated input and output ports, thus not using any internal tristate capabilities. Even if...
Verilog code to count Number Repetition
Assuming you have a clock and active low reset: module tracker( input clk, input rst_n, input [3:0] data_rx ); reg [7:0] count [0:15]; integer i; always @(posedge clk, negedge rst_n) begin if (~rst_n) begin for(i=0; i<16, i=i+1) begin count[i] <= 8'b0; end end else begin count[data_rx] <= count[data_rx] + 1;...
How to assign pins to natural type of ports in Xilinx
Unfortunately, the one place where you can't use type natural is top level ports, where they are mapped to physical device pins. This is because you need to connect each individual bit of the signal to its own pin, so you need some type that represents the signal as an...
Xilinx error while compiling hello world, missing library - Ubuntu 14.04
xilinx,ubuntu-14.04,microblaze
It seems like installing the package rpm fixed the problem - honestly i don't know why.
Does C++ runtime always require malloc()?
c++,malloc,xilinx,standard-library,bare-metal
Reliance of a program on malloc() can occur in both C and C++, even if the program doesn't directly use them. It is a quality of implementation matter for the compiler and standard library rather than a requirement by the standards. This really depends on how the both the compiler...
Type conversion in VHDL: real to integer - Is the rounding mode specified?
type-conversion,vhdl,xilinx,xilinx-ise,vivado
From IEEE Std 1076-2002 section 7.3.5 "Type conversions" The conversion of a floating point value to an integer type rounds to the nearest integer; if the value is halfway between two integers, rounding may be up or down. If you want something else, maybe functions in IEEE.MATH_REAL can be of...
Xilinx + small touch screen prototype path?
touchscreen,xilinx,prototyping
First: There are several types of cheap touchscreens: resistive and capacitive (intro from 3m). And under touchscreen I mean touch panels (digitizers) - the thin multilayer panels which feels touches, but don't display anything. Touchscreens can be combined with LCD/OLED screens to get display with touch capability. Resistive touchscreens are...
If statement using vhdl
As pointed out by Morten Zilmer, you need to terminate the if/else with an end if. Also there have been some missing semicolons. The code below should work. if (inc_dec='1') then if (r_reg=(M-1)) then r_next <= (others=>'0'); else r_reg+1; end if; elsif (inc_dec='0') then if (r_reg=(M-10)) then r_next <= to_unsigned(9,...
Why do I need to turn off IO buffers for my partially reconfigured module in Xilinx PlanAhead 14.7?
When you synthesize your top level design in Project Navigator you should enable the IO buffers so that your design can access the external ports, but your internal modules should not have them enabled. Normally, IO buffers are automatically turned off for internal modules, but in the case of partial...
Why does this code for incrementing an uint8_t include `& 0xFF`?
My guess is that this code was intended to work correctly even if value is not a 1-byte (8-bit) type. The bitmask 0xFF makes sure that only the last byte of the value is kept.
Signal led cannot be synthesized, bad synchronous description?
The error message appears to be complaining that you are using the output of the cnt counter as a clock. Instead you could use it as a toggle enable and clk as the clock: --process (clock, btn) process (clk, btn) begin -- if btn = '0' then if btn =...
How to create a test bench code for full adder?
Here's a good reference, one of the first that came up when I googled how to write a testbench. You should google first, give it an honest shot, then come back here with more specific questions. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Full_Adder_tb is end Full_Adder_tb; architecture Behavioral of Full_Adder_tb is...
ISIM only simulates until 61.215.000 picoseconds
I have run simulations much longer than this in ISIM, so this points at your code, I think. Two ways forward: Try another simulator, perhaps ghdl (free) and see if it reports a problem that ISIM doesn't. It is usually stricter (more standard compliant) than ISIM and can sometimes diagnose...
generic adder “inference architecture”: simulation error
vhdl,xilinx,modelsim,inference
The length of U is N+1 (0 to N) Changing U <= to_unsigned(add_all,N); To U <= to_unsigned(add_all,N+1); Will prevent a length mismatch between the left hand side and right hand side of the signal assignment in architecture inference of adder_n. The passed parameter to to_unsigned specifies the length....
What is the cause of Vivados 'synth 8-1027' error?
Vivado parses all files. Even those which are not used! My ISE project had a old backup file with a package named 'DMATest' inside it. This should explain why DMATest was reanalyzed and DMATest is not an entity - it was overridden by the package....
Does Quartus II support line.all?
See Quartus II VHDL Support, Section 14 Predefined language environment, the table entry 14.3, Construct TEXTIO, the rightmost column VHDL 1993 Support: Supported. File I/O cannot be synthesized; therefore, calls to TEXTIO functions are ignored. If you can't use TEXTIO for synthesis you could imagine a pointer to a line...
Why dynamic power consumption is always zero?
As Brian indicated in his comment, the reason your original power estimate had no dynamic power consumption was that when the design was originally simulated, it was simulated in a static state. That is to say, no elements of your design were toggling. The reason no elements of your design...
How to solve these warnings? | VHDL Programming
Complaining about dead/unused code WARNING:Xst:646 Signal <thirdaddress> is assigned but never used. Signal <secondaddress> is assigned but never used. Signal <firstaddress> is assigned but never used. This means these three signals are unused in your design. If you don't plan to use them in future, you can remove them ->...
Error in VHDL (Xilinx): failed to link the design
For the process failing part, it seems that Xilinx tool writers may have an issue try restarting them and if needed, your machine as well.
Why do I get no output at my VHDL multiplier?
Don't use a register with a load enable, use clock edge register. The iteration limit is a delta cycle limit in ISIM. Introducing a '1' in b you get a striking oscillator, a loop with delta cycle delays and inversion (the summing). Make num4, reg4 and reg8 clock edge driven...
How can I design VHDL modal in the following details?
q <= std_logic_vector(resize(signed(a), q'length)); The std_logic_vector doesn't represent an integer value, only an array of std_logic, so first you make it signed using signed from ieee.numeric_std.signed. A resize function is also defined in ieee.numeric_std for signed and unsigned, and it is applied to the signed value, with the desired length...
FPGA reached the limit of USB WireIns
If you have lots of data that you can stream, use a Pipe. If you want to access the data randomly, you'll have to use a multiplexer, controlled by a WireIn. Regarding efficiency, you'll have to specify what dimension of efficiency you are interested in, and what value is acceptable....