I have few unsigned, 8bits-wide number that i need to add/subtract together. Below the example:
h_tmp <= signed(r4(calc_cnt - 2) + r4(calc_cnt - 1) + r4(calc_cnt) +
r4(calc_cnt + 1) + r4(calc_cnt + 2) -
r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) -
r2(calc_cnt + 1) - r2(calc_cnt + 2));
I know that a 13 bit wide result is ok for the numbers that I have, so i defined h_tmp as a signed (12 downto 0). Now, after synthesis I have the following warning
Width mismatch. <h_tmp> has a width of 13 bits but assigned expression is 8-bit wide.
It seems that the synthesiser inferred a 8bits-wide result of the calculation, what have I done incorrectly?
Best How To :
Assuming the addition/subtraction (
-) is based on the
ieee.numeric_std package (or
ieee.std_logic_unsigned), the result length of an addition/subtraction is that of the longest argument.
So if all your arguments in the addition/subtraction chain are 8 bits long, then all the additions are made as 8-bit additions/subtractions, even through you assign to a 13-bit result.
So start the addition/subtraction chain with resize of the first argument to the length of the result, like below for
h_tmp <= signed(resize(r4(calc_cnt - 2), h_tmp'length) + r4(calc_cnt - 1) ...
ieee.std_logic_arith package use