The IA-32 architecture implements PAE to increase it's address space from 32 bits to 36 bits, this is done by dividing the page table in a three-level scheme.
Page directory table -> page directory -> page table -> 4-kb page
How is the increase from 32 to 36 bit address space achieved where do the 4 extra bits come from?
Best How To :
The physical address space can be 36 bits. The linear address space is always 32 bits in IA-32.
Its achieved by increasing the size of the page directory pointer table entries, page directory entries and page table entries. They are all 64 bits with PAE paging enabled.And actually with PAE you can address up to 52 bit physical address space.
To store the 36 bit physical address of 4KB page you actually need less than 36 bits because you know that the address will end up with 12 zeroes (2^12B=4KB) since the address is page aligned. So you actually need 24 bits to store it.
The problem with storing it for paging in 32-bit mode is that the table entries are only 32 bits and 12 bits of them are reserved for flags and internal CPU usage.So you only have 20 bits left which is not enough for the purpose.You can only use those 20 bits to store 32 bit physical address of a page.
Some CPUs however support extension called PSE-36 which allow to address physical address space up to 40bit in 32-bit paging mode with 4M pages enabled. The paging structure is the same (32 bit entries) but some of the unused bits in the entries are used to store the rest of the physical address. (Note that for 4MB pages the last 22 bits of the address end up with 0 because 2^22=4MB so you need 22 bits less than the actual physical address to store it).
Edit : here is a picture from the IA-32,Intel64 Software developer manual. This is how the page structure entries look in 32-bit paging mode
Here is how they look in PAE mode :